Analysis of low power 7T SRAM cell employing improved SVL (ISVL) technique

With the increase in demand for low power memory, this is achieved by reducing the leakage currents. Power dissipation mainly occurs due to leakage currents of different forms such as Sub threshold & Gate leakage etc. and need to reduce these currents. This work mainly aims at design of low power 7T SRAM Cell by employing Improved Self Controllable Voltage Level (I-SVL) circuits. Simulation results show that there is enormous leakage current reduction in Improved Self Voltage Level method than Upper Lower-SVL 7T (UL-SVL) & Basic 7T SRAM Cell. I-SVL method resulted in 60% reduction of leakage current compared with UL-SVL SRAM 7T Cell and 68% reduction in comparison with Basic 7T SRAM cell. The entire Simulation is carried on 180nm CMOS technology, in Virtuoso platform of Cadence tool with a supply voltage of 0.7V.