FPGA based hardware implementation of hybrid cryptographic algorithm for encryption and decryption

In this paper, a hybrid encryption algorithm is proposed. The RSA (Rivest Shamir Adleman) public-key standard has been used along with AES (Advanced Encryption Standard), a symmetric key algorithm, thereby reinforcing the RSA architecture as well as giving rise to a much more secure encryption algorithm. This hybrid design is implemented on Modelsim to obtain the simulation results and then synthesized using Xilinx ISE platform and targeted on a FPGA. In the proposed hybrid system, to provide extra security and to achieve much stronger encryption, the AES key is also encrypted using RSA algorithm along with the encryption of plaintext by AES. This virtually provides a double layer of the security perimeter. For the decryption, the RSA public key is used to decrypt the AES key and then using this key, the original plaintext message is obtained.