Leakage current optimization in 9T SRAM bit-cell with sleep transistor at 45nm CMOS technology

SRAMs have large number of applications in high speed registers, microprocessors, small memory banks, general computing applications etc. Therefore delay, power, speed, leakage current and stability are the main concerns. These parameters are in trade off to each other. This paper focusses on the leakage current, power and stability in 9T SRAM bit-cell. In the proposed and modified 9T SRAM bit-cell works as a sleep transistor. As power is proportional to V²_dd [1], the power is reduced by 32.3%. There is a significant reduction of 59.3% of leakage current. The stability parameter SNM is calculated which shows that stability is increased by 18.9%. The static power is also reduced by 98.7% because of the stacking of PMOS, PMOS and NMOS transistors. The 9T SRAM cell with sleep transistor is compared with conventional 6T SRAM cell. The simulations are done using Cadence Virtuoso tool with gpdk 45nm CMOS process technology at 0.6V, 0.7V and 0.8V power supplies.