Design and simulation of multimaster ahblite bus interconnect

This paper implements an Advanced Microcontroller Bus Architecture (AMBA) AHBLite bus interconnect fabric using multi layer interconnect bus matrix. This interconnect has four masters and sixteen slaves thus makes it a multi-master AHBLite. We can enable or disable each slave for each master using the control parameters. Those slaves which are not used by any master, gets optimized away after synthesis. The arbiter logic used is Round robin algorithm. We can combine two or more slaves to get one additional slave interface for connection. This feature is useful when a master wants to access a number of resources through a single slave interface. It also provides remap functionality for first master. When remap is high, slave 0 and slave 1 memory space are swapped. The complete design is realized using Verilog HDL and simulated using ModelSim SE 10.4c and synthesized using Synplify to obtain resource utilization. The results obtained shows that the design uses very less resources of the device.