Design and implementation of high speed modified booth multiplier using hybrid adder

Multiplier is one of the most desirable component in most of the processors designed today. The speed of multiplier determines the speed of the processor. So there is a need of high speed multiplier. In this paper, a novel method for Multiplication is proposed by combining Modified Booth algorithm, Wallace tree architecture and Hybrid adder design. Modified Booth Multiplier reduces the number of partial products and has least latency as compared to other multiplier designs. Wallace Tree increases the speed by parallel addition of partial products. Adders play an important role in addition of partial products. If the speed at which the addition operation is performed is increased than the overall speed of the multiplier design will increase. So the main focus in this paper is to increase the speed of the adder. A novel hybrid adder design is used in the multiplier design which, has less delay and occupies less area. Area, delay and power complexities of the proposed Multiplier design are reported. The proposed Modified Booth Multiplier design shows better performance compare to conventional method using Carry LookAhead Adder and has advantages of reduced area overhead and critical path delay. The proposed multiplier design has been synthesized using Xilinx ISE 10.1 design tool and simulated using ModelSim15.7g. The programming language used is Verilog HDL.