TCAD based performance analysis of junctionless cylindrical double gate all around FET up to 5nm technology node

In this paper, a cylindrical double gate-all-around technology is merged with junctionless technology to maximize gate control as well as to avoid loss due to the formation of junction in the source-channel-drain region. This advancement allows downscaling a junctionless cylindrical double gate all around FET (JL-CDGAA FET) up to 5nm channel length with acceptable performance in many of its parameters. A comparative study between JL-CDGAA FET and GAA FET is also presented in this work.