Area-efficient high-speed hybrid 1-bit full adder circuit using modified XNOR gate

A hybrid 1-bit full adder design is presented here using modified 3T-XNOR gate to improve the area and speed performance. The design is implemented for 1-bit full adder and then is scaled to 32-bit adder. Combination of CMOS and transmission gate logic is used to enhance the performance in terms of area, delay and power. The performance of the proposed design is evaluated through the simulation analysis in 90-nm technology with 1.2v supply voltage. The effect of scaling on the overall performance is also analyzed through the performance evaluation of 1-bit and 32-bit adder. The performance of proposed design is also compared with conventional design to verify the effectiveness in terms of area, power, delay.