Novel ICP Plasma Etching for Backside TSV

“Cloud & Edge” computing is important to realize the IoT society. IoT devices are expected to expand rapidly in the next few years. The number of IoT device was 24.2 billion in 2015, but it is predicted to be 53 billion in 2020[1]. In the mega data center, a huge amount of data is processed, and the devices used there are strongly required high speed, low latency and low power consumption. Innovation is expected and that will be realized by 3D packaging of high performance CPU and storage [2]. Recently, demand of high performance S SD for data center has been rapidly increasing and structure of NAND flash memory is changing 2D to 3D. In addition to the 3D memory cell, 3D chip stacking using TSV is important [3]. For edge computing, 3D heterogeneous integration for M2M/sensor module are key technologies [4]. 3D packaging is indispensable technology for realizing the IoT society, and back side via is the most effective means from the viewpoint of cost and reliability [5]. We have been developing TSV process by `scallop-free' etching [6]. Thus, in this study, we focused on the backside TSV and have been developing TSV process and hardware. In non-Bosch etching, etching and sidewall protection are performed at the same time, so that the ratio of fluorine radical contributing to etching and oxygen radical contributing to sidewall protection greatly affects the etching shape. We focused on the difference in Oxygen ratio depending on frequency and developed a new plasma source combining RF and LF. This plasma source enables uniform etching in the wafer whether the shape is vertical or tapered.