On-chip layout optimization of synchronous DC-DC buck converter for EMI reduction

In this work, we analyzed the noise occurring at the switching node of a synchronous DC-DC converter in on-chip level according to the metal layers and optimized the layout to reduce that noise. By sweeping the metal width and changing the arrangement of the pass transistor, the peak voltage level and the maximum of the near field were estimated through HFSS simulation. As a result, alternately arranging the PMOS and NMOS pass transistor shows lower peak voltage level. Moreover, there is an optimum metal width to reduce near field occurring at the switching node.