VLSI implementation of low power micro cordic processor for real time antenna array applications

This paper describes a new parallel micro cordic processor architecture most suitable for low power applications. In the proposed architecture parallel micro cordic algorithm was realized for the real time antenna array applications. Implementing this algorithm in the proposed architecturally modified micro cordic processor has the advantage of replacing the multiplication operations with shifting and adding logic and arithmetic operations. Thus it has less utilization of memory. A 2×2 Microsrtip patch phased array antenna was designed for transmission purpose. This low power micro cordic processor was interfaced to the Microsrtip patch phased array antenna. By using the proposed architecturally modified micro cordic processor the coordinate values were calculated for angular rotation of the Microsrtip patch array type antenna at a reference angle of 30 radians and the simulated results were studied. The micro cordic processor executions were verified using Xilinx and modelsim software. The information from micro cordic architecture was fed to the designed antenna for the angular rotations and results were evaluated at a reference angle of 30 radians. The VSWR, gain and return loss of the Microsrtip patch phased array antenna for the taken reference angle 30 radian were 2.8839, 1.9469dB and -28.5dB respectively.