Implementation of shift register using pulsed latches

Low power and less area in an electronics devices having very high demand in the world because of user want to fast mobility with less power consumption and also not compromising with the area. By using multiple stages of flip flop and latches to compare area and power. The main objective to designing a flip-flop with respective pulse latches is consume less power. For solving timing problem a new technique is use, in which of pulsed latches and multiple non-overlapping delayed version of pulsed clock signal are uses. In this system, single clock pulse signal uses and combine this latches to multiple sub-shifter register and further for only a limited period of time storage latches. In this minimum number of clock pulse signal use by groping latches to multiple sub shift register and using short-term storage latches. 8, 16, 32, upto 256-bit shift register using pulsed latches was fabricated using 180nm cmos process with vdd is 1.8V. This proposed system implementation by using cadence tool.