EDR-BLE transmitter using power gating technique in 45 nm technology

In this paper, the Enhanced Data Rate Bluetooth Low Energy (EDR-BLE) transmitter design in 45 nm technology is thoroughly detailed by explaining the on-chip RF circuitry modules like Phase Locked Loop (PLL), Quadrature Phase Shift Keying (QPSK) modulator, RF amplifier and power management circuit. Integration of sub modules like Phase Frequency Detector (PFD), Charge Pump (CP), loop filter, Voltage Controlled Oscillator (VCO) and divider result into the PLL block. Third order low pass filter is designed as loop filter to reduce magnitude of the reference spur sidebands. True Single Phase Clock (TSPC) architecture is used to design the divider as it has the advantage of a higher operating frequency. It also reduces the power consumption and propagation delay. QPSK modulation technique is incorporated in the proposed design of EDR-BLE transmitter. Power gating technique is handled in power management circuitry to function the modules with low power consumption. It is one of the optimum solutions provided for proper power management. Construction of the transmitter consisted of producing a detailed schematic of each modules constituted in the design. Finally, the output of the schematic design of EDR-BLE transmitter produced a clean signal for both the in-phase and quadrature phase signals. It is visualized with necessary terminologies in the final transient analysis response of the EDR-BLE transmitter.