Architecture and performances comparison of Network on chip router for hierarchical mesh topology

Recently, Network on chip (NoC) has emerged as a good solution for future complex System on Chip (SoC). As opposed to bus technology, NoC allows the communication of hundreds or thousands of cores (processors, memories...) on a single chip. This work aims at providing comparison and performance analysis of three regular NoC topologies. We present the different pipeline stages of the proposed router which is the backbone of the NoC. The proposal supports the hierarchical mesh topology and uses a minimal routing algorithm to avoid deadlocks and a priority based arbiter to satisfy the quality (QoS) of service expected by the NoC. Results are presented and compared with other works in terms of maximal clock frequency, area, power consumption and peak performance.