A novel bit-level characterization methodology to benchmark the FinFET based SRAM performance under the influence of leakage current

Presence of any erroneous leakage current source, due to any intrinsic or extrinsic device failure, can severely impact the 6-Transistor (6T) SRAM performance. This study introduces a ‘Pseudo-Leakage’ (PL) current source in the SRAM 6T circuit and takes a pragmatic approach to analyze the possible impact on the SRAM performance matrices which are affected by such leakage issues. All key factors such as SRAM static noise margin (SNM), cell driving current (Icell) and ‘high’ (‘1’) node voltage stability are studied in this work. Finally, the SRAM speed and the crucial SNM Initial-operation-Voltage (SNMIV) are estimated in the presence of such leakage source.