A physics-based Quasi-2D model to understand the wordline (WL) interference effects of junction-free structure of 3D NAND and experimental study in a 3D NAND flash test chip

3D NAND is usually designed with the charge-trapping (CT) device, arranged in a “junction-free” structure where the transistors are serially connected without a N+ diffusion junction in between them. This paper provides a physics-based quasi-2D model and several analytical equations that can readily simulate the surface potential variation inside the junction-free 3d NAND. It is clarified that the operation of junction-free 3D NAND is dominated by the continuity of surface potential derived by the Poisson equation. The neighbor WL pass-gate voltage (Vpass) and Vt interference effects are both the outcome of surface potential continuity that results in the “non-local” behavior of surface potential that can be affected be the neighbor and even far neighbor cells. It is not caused by the fringe field effect or capacitive coupling. From our simulation, the WL interference effect can be suppressed by using the extreme-thin body device (Tsi < = 6nm) because of shorter DIBL characteristic length that can confine the surface potential. We've studied the WL interference effect in a 32Gb 16-layer single-gate vertical-channel (SGVC) 3D NAND Flash test chip using the thin-body Tsi = 6nm device. It is found that the far-neighbor WL (n-2) cell also contributes to the WL interference effect as well. Experimental data show that we can use lower BL sensing voltage to suppress the WL interference. A practical WL iterating programming method can greatly cancel the WL interference effects and produce tight programmed Vt distribution for multi-level cell (MLC) operations.