Latency reduction with short processing time and short TTI length

Latency is an important component in fifth generation (5G) study. In this paper, we focus on the latency reduction with short processing time and short TTI length. The maximum time advance (TA) and transport block size (TBS) are introduced to shorten the processing time. Short processing time with frame structure unchanged results into less standardization efforts but is hard to support stricter requirement on latency such as less than 1ms. Short TTI length is taken into account and 2-symbol length can achieve a tradeoff between overhead and performance gain. A short PDCCH design is proposed and a two-stage DCI is introduced to handle the large number of blind decodes within a subframe due to the change of TTI length. Both short processing time and short TTI length are an effective way to reduce latency.