Abstract:
This letter presents a new angle for the design of negative-capacitance FETs, where the target is not a steep sub-threshold swing, but instead an enhancement of the devic...Show MoreMetadata
Abstract:
This letter presents a new angle for the design of negative-capacitance FETs, where the target is not a steep sub-threshold swing, but instead an enhancement of the device transconductance in near- and above-threshold region. The new design is robust against an undesired complete ferroelectric switching and the resulting onset of hysteresis, and it is validated using numerical simulations, calibrated against recent experimental data, and for an ultra-thin body, double-gate FET architecture.
Published in: IEEE Electron Device Letters ( Volume: 39, Issue: 4, April 2018)