Asic design of low power VLSI architecture for different multiplier algorithms using compressors

In most of the digital systems, adders and multipliers are the fundamental components in the design of many applications domains such as a digital signal processing especially for multimedia application such as graphics 3D depends on extensive number of multiplication, scientific and numerical applications. This paper proposes a novel Compressors for low power VLSI architecture of different multiplier Algorithms and their ASIC design. Purely combinational logic is used in the design of these multipliers. The partial product bits are obtained by ANDing of both multiplier and multiplicand bit. Then the partial Products are summed using compressor technique. In this paper the proposed novel 4-2 and 5-2 compressors architecture achieve low energy consumption, when used for different multipliers. All the proposed architectures are designed using Verilog HDL and are simulated using Xilinx tool for functionality verification. The physical verification is also done using the 180nm tsmc technology library, operating in slow (balanced-tree) conditions generated by Encounter (R) compiler. In particular, the results were compared with conventional multiplier algorithms and found that the proposed compressors when used in multiplier algorithms are more efficient in terms of power.