The MapReduce application of matrix multiplication implemented on field programmable gate arrays

Data intensive computations in data centers are performed by an increasingly popular programming framework named MapReduce. An advantage of this framework is that the algorithm is divided into simple tasks that enables the exploitation of its parallelism. A great variety of processing elements architectures, such as shared memory systems, clusters of computers and heterogeneous systems, have accommodated applications of the MapReduce framework in order to enhance its robustness and efficiency. Field Programmable Gate Arrays (FPGAs) are known for implementing algorithms while providing higher parallelism compared to their software counterparts. The mapping of a MapReduce framework on specialized hardware is proposed here. The proposed FPGA architecture is using a pipeline principle in order to alleviate the need of large memory resources. The proposed system was analyzed implementing a basic application, namely matrix multiplication.