Configurable-accuracy approximate adder design with light-weight fast convergence error recovery circuit

Approximate computing has recently introduced a new era of low-power and high-speed circuit designs. Recent efforts in the domain of configurable-accuracy approximate designs have proposed substantial performance gains and energy savings by allowing performance-energy-accuracy trade-offs. In this paper, we propose a configurable-accuracy approximate adder with new light-weight error detection technique. This is followed by significance-driven error correction stages during run-time. The correction starts by recovering the higher magnitude errors at premier correction stages, which results in fast convergence and higher precision outputs. Compared to other equivalent approximate adders, the proposed design has drastically reduced the logic counts used for error detection process; hence, achieving lower overhead of silicon area and improving the energy-efficiency of the adder design with faster convergence to the exact results. A number of different bit-widths of the proposed adder (32-bit to 256-bit) are designed in Verilog and synthesized using Synopsys Design Compiler. Our post-synthesis experiments showed significant reductions of 12% and 10% for Dynamic and Leakage Power respectively, and 8% in the silicon area for the design with full correction stages. Moreover, the proposed adder with large bit-widths has reserved these reduction ratios while presenting better scalability overhead. Additionally, our low overhead proposed design has presented the chance to be improved in terms of increasing accuracy to reach 100% exact results as accurate conventional adder at the final correction stage.