Performance analysis of 1-bit full adder using different design techniques

A fast and power-efficient full Adder plays key role in electronics trade especially performing arithmetic operations in microprocessors, digital signal processing (DSP) and image processing. Full Adder is such a significant element which contributes substantially to the total power consumption of the network. In this paper, 1-bit Full Adder has been designed which is then analyzed. The leakage power consumption has been done in the circuit using different technologies such as 120nm and 180nm. The designed circuit has shown a incredible reduction in the consumed power of 97.8% and an increase of 12.7% in consumed area compared to GDI full adder in 120nm foundry. By using DSCH2 and MICROWIND2 tools, the designed 1-bit complete adder are compared in phrases of leakage power consumption and surface area.