A single phase fault tolerant multi level InverZter topology

In recent years, attention is drawn towards the reliability of the multi-level inverter topologies. Multi-level inverters incorporates a large number of semiconductor devices which are the weakest link in the power inverting stage. Therefore fault tolerance becomes an important research aspect especially in the applications where human intervention is most difficult. In this paper, a novel topology is proposed which is fault tolerant to both single switch and multi-switch fault. The proposed topology also keeps the device count into consideration. In comparison with the recent topologies, the proposed topology offers better result as will be explained in the later part of the paper. The validity of the proposed topology is verified through MATLAB simulation.