Optimization of InSb QWFET layer structure for high-speed and low power nano electronics applications

The parameters of InSb quantum well field effect transistor (QWFET) layer structure such as spacer layer, barrier layer, quantum well (QW) thickness and doping density in the barrier layer have been revealed using self-consistence quantum corrected Schrödinger Poisson (QCSP) solution. The optimized value of the spacer and barrier layer of the InSb QWFET are found to be 25 and 45 nm, respectively. The quantum well thickness and doping density in the barrier layer of the InSb QWFET have also been optimized 20 nm and 1 × 10¹² cm⁻² respectively. The results are employed in the proposed structure and an optimized InSb QWFET has then been calculated at room temperature with a very high electron mobility 3.27 m² V⁻¹ s⁻¹ and density 2.36 × 10¹⁵ m⁻² at gate voltage, Vg = 0V. The two dimensional electron gas (2DEG) in the 20 nm QW is completely depleted by a very small Vg= −0.47 V (pinch-off voltage Vp). The optimized InSb layer structure has significant implications for realizing InSb-based high-speed and low power depletion-mode QWFET for nanoelectronics applications.