Influence of device performance of Sub-10 nm GaN-based DG-MOSFETs over conventional Si-based SG-MOSFETs

The investigation was performed on sub-10 nm GaN-based double gate (DG) MOSFETs over conventional Si-based single gate (SG) MOSFETs. The projected device has been designed for L
_g
= 7.3 nm and 9.3 nm gate length of GaN-based DG-MOSFET by using Silvaco ATLAS followed to the NEGF method. The primary goal was to mitigate the SCEs (short term of short channel effects) implementing double gate (DG) over a single (SG). The investigation was on the sub threshold slope (SS), ION, drain induced barrier lowering (DIBL) and switching behavior of the electric field based on the consequence of simulations. GaN-based DG-MOSFETs shows better improvement results than conventional Si-based SG-MOSFETs. GaN-based DG-MOSFET has drawn the attention over conventional Si-based SG-MOSFETs due to excellent on-state current and fast switching performance. The impact of achievable mobility on device design and performance claims GaN-based DG-MOSFETs as a promising candidate for VLSI applications.