Effect of Lsg/Lfg ratio variation to the IV curve of split-gate 1st generation superflash

A simulation involving SST 1^st generation splitgate flash memory cell has been taken. We investigate the effect of different L_SG to L_FG ratio to the result of IV curve as well as floating gate's average electron density during a program-erase cycle. We use 0.37, 0.50, and 0.65 L_SG/L_FG ratio. It turns out that in general, an increase in L_SG/L_FG ratio (0.37 to 0.50) will give result in increasing program threshold voltage and at the same time, lowering the erase threshold voltage with exception of the third ratio (0.65). The results are then confirmed by inspecting floating gate's average electron density throughout program-erase cycle which also show a significant rise as L_SG/L_FG increase. It will be shown that the programming threshold voltage is determined mainly by average electron density in floating gate, while the threshold voltage shift is determined by the difference between floating gate's average electron density in programmed states and erased states.