Fast Built-In Redundancy Analysis Based on Sequential Spare Line Allocation | IEEE Journals & Magazine | IEEE Xplore

Fast Built-In Redundancy Analysis Based on Sequential Spare Line Allocation


Abstract:

Built-in redundancy analysis (BIRA) is widely used for memory yield improvement. However, increases in fault occurrence probability inevitably lead to the use of various ...Show More

Abstract:

Built-in redundancy analysis (BIRA) is widely used for memory yield improvement. However, increases in fault occurrence probability inevitably lead to the use of various spare lines to achieve a high repair rate. Generally, it is difficult to apply conventional BIRAs for memories with various spare lines because they focus on a simple spare structure. Therefore, this study examines a BIRA that focuses on a various spare lines structure. The proposed BIRA achieves a high repair rate through the use of various spare lines. Although long analysis time is typically required due to the use of various spare lines, the proposed BIRA solves the problem through sequential spare line allocation. Additionally, it achieves hardware overhead reduction through a simple analyzer. These advantages of the proposed BIRA are demonstrated experimentally.
Published in: IEEE Transactions on Reliability ( Volume: 67, Issue: 1, March 2018)
Page(s): 264 - 273
Date of Publication: 09 January 2018

ISSN Information:

Funding Agency:


Contact IEEE to Subscribe

References

References is not available for this document.