A survey on different modules of low-power high-speed hybrid full adder circuits

In this paper, a review study and analysis of designs for 1-bit hybrid full adder is demonstrated. The hybrid full adder is decomposed into three sub-modules. For each sub-module, different designs are simulated and analyzed. Each module exhibits different speed, power consumption and area. Ten different 1-bit hybrid full-adder cells are created by combining possible arrangements of different designs of sub-modules. Each of these hybrid full adder cell differs from one another in terms of transistor count, average power dissipation and delay. All the circuits have been designed using CADENCE Virtuoso tool at 45-nm technology and simulation is done using SPECTRE simulator. Comparison of performance parameter like power dissipation and delay is done with the existing standard adder cells transmission gate adder, complementary pass-transistor logic (CPL), and conventional CMOS adder.