Towards SRAM leakage power minimization by aggressive standby voltage scaling — Experiments on 40nm test chips

On-chip SRAMs dominate the leakage power of IoT devices. Aggressively scaling down SRAM standby voltage reduces leakage power while sacrificing reliability of data retention. Based on stationary spatial on-die distribution of retention bit-flip errors, we propose to apply a static error protection strategy as a simple, fast and low-cost remedy for aggressive standby voltage scaling of SRAMs. Experiments on 40nm test chips are presented, including a comparison to the conventional ECC schemes in terms of error protection and area/power overheads.