Cross-layer refresh mitigation for efficient and reliable DRAM systems: A comparative study

DRAM is a crucial component in computing systems, and is expected to be even more important as data-intensive applications become more prominent. A key challenge in advancing DRAM technology is the growing cost of refresh operations, which can impose a large impact on the energy efficiency of DRAM modules. Existing refresh mitigation techniques all require hardware modifications, which may be undesirable. In this paper, we make two major contributions. First, we present a new cross-layer refresh mitigation approach that takes into account both DRAM retention time characteristics and application behaviors. The main ideas are: (1) uniformly lower refresh rate to improve DRAM energy efficiency, (2) utilize a combination of system-level memory tests and ECC/scrubbing to detect and correct errors resulting from the reduced refresh rate, and (3) perform software-based memory repair so that DRAM cells in which errors occur because of the reduced refresh rate are not mapped to application space. Our approach reduces refresh power by 98.6% and improves overall DRAM energy efficiency by up to 37.7% without sacrificing reliability, at the low price of a small reduction in main memory capacity. Second, we perform thorough experiments and analysis to compare our cross-layer approach with prior work. In general, our approach achieves better or similar power benefits, but it does not require any modifications to the hardware.