Layout-aware 2-step window-based pattern reordering for fast bridge/open test generation

Advances in semiconductor device manufacturing technology, which have enabled reduced feature size and higher integration, have resulted in a gap between the defect level estimated at the design stage and that reported for fabricated devices. As one possible strategy to control test quality and cost, the authors have proposed weighted fault coverage estimation. In this study, we propose layout-aware, fast and compact test pattern set generation considering both bridge and open weighted fault coverages. The proposed scheme applies two-step test pattern generation where only second pattern set is reordered with fixed size of search window, achieving O(n) computational complexity. Compared to simple greedy-based reordering, the experimental results indicate that the proposed scheme with a 10% initial target fault size and a fixed small window size achieves approximately 100 times runtime reduction with further in exchange for about 5% pattern count increment.