Soft error considerations for deep-submicron CMOS circuit applications

The increasing importance of characterizing both memory arrays and core logic when estimating soft error FIT (failure in time) rates has been demonstrated using test-circuits, a 21264 Alpha microprocessor, and simulations. The reduction of operating voltage has been determined to increase the soft error rate exponentially at 2.1-2.2 decades/volt. Based on the SIA roadmap for CMOS scaling trends, meeting FIT rate requirements in the core logic will pose many challenges in the imminent future.