Reusable design of run length coder for image compression application

In this paper, we describe the interface specification and core block design methods for a run length coder of video compression application. It offers high performance and many features to meet multimedia, and digital video applications. We designed the VLSI architecture of the run length coder using VHDL. This design can achieve a high performance for the video coder and is based on H.263 Recommendation. The format of the outputs is compatible with the stream of the variable length coding. The run length coder is implemented by the register transfer level (RTL) of VHDL. The designed block is synthesized by Compass synthesis with 0.5 /spl mu/m CMOS, 3.3 V, technology and reuse as core IP (Intellectual Property) of H.263 and MPEG4 application. The run length coder block contains 4,000 logic gates and a total 1,536 bits of static RAM. The fully synchronous design allows for fast operation while maintaining a low gate count. The core will reuse for multimedia system and digital video applications.