A calibration-free 3.0 V 12-bit 20 MSPS A/D converter

A calibration-free 3 V 12-bit 20 MSPS pipelined analog-to-digital (A/D) converter was implemented using 0.35 /spl mu/m CMOS technology. The proposed hybrid capacitor switching technique of two feedback capacitors is applied to improve the linearity which is limited by component mismatch depending on the process. Since the proposed technique can be implemented by simple circuits compared with previous self-calibration techniques, it allows smaller area and lower power consumption and it is applicable to general pipelined architectures. Other technique proposed to improve the linearity is a capacitor array layout scheme which is insensitive to the parasitic effect of capacitor top plates. The A/D converter occupies a die area of 2.57 mm/sup 2/ (1260 /spl mu/m/spl times/2040 /spl mu/m) excluding pad ring and dissipates 135 mW at a 20 MHz clock rate with a 3 V single supply. Typical differential nonlinearity (DNL) and integral nonlinearity (INL) are /spl plusmn/0.72 LSB and/spl plusmn/1.22 LSB, respectively.