High voltage NPN-bipolar transistor using P/sup +/-buried layer in BiCMOS process

An easy to implement high voltage NPN transistor is integrated in a low voltage (LV) thin (4.5 /spl mu/m) epi-layer BiCMOS process. In this high voltage (HV) bipolar transistor, the conventional N/sup +/-buried layer of the collector is replaced with a P/sup +/-buried layer. The breakdown voltage is higher than 90 V. High current gain (>140), high Early voltage (>500 V), and high frequency response (>1.3 GHz) are also obtained.