Design for test of Mbit DRAMs

The authors describe a novel design for test of DRAMs (dynamic random-access memories) which speeds up testing during wafer sort and final test, even after repair by redundant bit lines. This concept is based on internal parallel and marginal tests initiated by a JEDEC (Joint Electron Device Engineering Council) conformance standard. Test sequences of 1-Mb and 4-Mb DRAMs were analyzed to determine the applicability and utility of the proposed test methods. Total test time savings range between 50% and 75%, depending on the memory size. The additional chip size is <1% of the total chip area.<>