Impact of parasitic coupling on multiline TRL calibration

On-wafer measurements of any Device Under Test (DUT) usually require the application of a calibration algorithm to eliminate unwanted but unavoidable effects due to the probe tip properties, the probe pad, the neighboring structures on the wafer and instrumentation. The calibration is to remove their influence and to reveal the properties of the DUT itself. However, the calibration process is sensitive to parasitics of the probe environment and to the arrangement of the calibration lines on the wafer. This paper describes, for the case of thin-film microstrip lines, which deviations in the results must be expected and which basic rules should be followed to obtain a layout with minimum error using multiline Thru-Reflect-Line (TRL) calibration.