A 2 GS/s 118 mW digital-mapping direct digital frequency synthesizer in 65nm CMOS

This paper describes a Digital-Mapping Direct Digital Frequency Synthesizer consuming only 118 mW when operating at 2 GS/s in 65nm CMOS. The active area is 0.142 mm² with an accumulator size and amplitude resolution of 24 and 10 bits respectively. The Spurious-Free Dynamic Range is better than 41 dBc for synthesized frequencies below 750 MHz and 30 dBc over the entire Nyquist bandwidth. The Power Efficiency reaches 59 mW/(GS/s) by implementing a Complementary DualPhase Latch-Based architecture. Prototypes encapsulated in a 144-pin Low-Profile Quad Flat Package were employed during measurements. The achieved FoM is 542 GS/s · 2^(SFDR/6)/W.