Analytical study of high performance flip-flop circuits based on performance measurements

In designing synchronous circuits and memory elements, Flip-flops (FF) play an integral role. In the present era, the demand of area efficient, lesser delay, and faster devices are the major concern. This paper present the comparative study of Flip Flops in terms of area and delay. The problem of device size is very dominant today because the demand for small device size along with lesser number of transistors is increasing. And also for implementing a circuit, comparatively less number of transistors are preferred in comparison to conventionally used number of transistors, as it results in lesser number of switching activities. And smaller delay is preferred as it results in faster device along with faster response time of device. Hence, in this paper, the comparative study of various flip flops using The Clocked CMOS (C
²
MOS) register, True Single-Phase Clocked Register (TSPCR), Self-Gating Flip Flop, Static Flip Flop is done. The reduction in the delay is done by properly changing the size of transistor and alteration in the value of voltage. The circuits are simulated and correlated using 45nm technology.