Enhancing analog performance and suppression of subthreshold swing using hetero-junctionless double gate tunnel FETs

In this paper, we investigated a new device, Hetero-junctionless (H-JL) Double Gate Tunnel Field Effect Transistors (DGTFET) with high-k. III-V semiconductor material (like InAsSi) gives excellent performance when InAs uses at source side, because of low band gap it reduces the potential barrier height of source-channel interface causing maximum carriers are fastly tunneled across the source to drain in ON state whereas Si, at the drain side as higher bandgap increasing the barrier height of drain channel interface causing lower quantum tunneling occur, as a result good ION/IOFF ratio. The InAs-source JLDGTFET with high-k (Hfo₂) at 20 nm channel length provide tremendous characteristics with high I_ON/I_off ratio, lower point subthreshold swing (SS) and lower average SS at room temperature. The 2D simulation study of proposed device is done using sentaurus TCAD tools.