Design of a 0.52 mW −141 dBc/Hz and 450 MHz frequency synthesizer using low power and low phase noise current reuse VCO

This paper presents the design of a frequency synthesizer using phase locked loop (PLL) in a standard 130 nm CMOS technology with the supply voltage of 1.2 V. The low power and the low phase noise based current reuse VCO (CRVCO) and the frequency divider have been used to design the frequency synthesizer. The designed CRVCO gives a low power and a low phase noise performance. The designed PLL consumes 0.52 mW of power with −141 dBc/Hz of phase noise at 10 MHz offset and FOMpower of 1.33 mW/GHz. The PLL shows satisfactory performance for −40 °C to 125 °C with various process corners of transistors.