MIMO receiver and decoder using vector processor

The proposed vector processor has single precision floating point adder, floating point multiplier functional units and vector load store unit. The processor consists of five vector registers of 8-words; each word is of 32 bit. It also has 32-bit scalar registers. To increase the performance, pipelining along with vector chaining techniques are implemented. Processor architecture is implemented on ISim simulator using Xilinx. To analyze the performance of the proposed vector processor for number of instructions and speed with respect to scalar processor, 4×4 MIMO Receiver and MIMO Decoder application is demonstrated on the implemented vector processor.