Fault resistant encryption system using high speed AES algorithm on FPGA

In confidential data transmission data security is an important factor. Advance Encryption Standard is symmetric cryptography standard used for confidential data transmission. However, some faults are injected during implementation of AES to reduce its reliability and may cause information leakage. Fault detection scheme includes the details of each transformation in AES algorithm. Simulation results shows outputs of encryption and decryption process and flag error shows the state of faults that is detected or not detected. After fault detection one operation is performed that is redundancy check. Detected error or fault is corrected using redundancy check. The scheme is implemented using FPGA platform.