Low power high performance carry select adder

Carry Select Adder (CSA) is faster than any other adders used in many data-processing processors to achieve arithmetic functions speedily. By observing the structure of the CSA, it is clear that there is way for reducing the delay and power consumption. This work uses a sophisticated and efficient gate-level modification to significantly reduce the delay and power of the carry select adder. From the structure of the CSA, it is clear that there is scope for reducing the delay and power consumption in the CSA. Based on this modification 8-, 16-, 32-, and 64-bit CSA architecture have been developed and compared with the regular CSA architecture. The proposed design has reduced delay as compared with the regular CSA with only a slight increase in area. This work evaluates the performance of the proposed designs in terms of delay, area, power, and their products by hand with using tools like synopsis (VCS), Xilinx ISE. The results analysis shows that the proposed CSA structure is better than the regular CSA according to delay.