An efficient hardware realization of diamond search algorithm for motion estimation task in video compression applications

This work presents an efficient hardware realization of diamond search motion estimation algorithm using adder compressor units. The main advantage of this kind of hardware is its large quantity of processing modules (PM) which are employed to determine the sum of absolute difference distortion metric. Processing units are composed of large quantity of adders to calculate the summation of absolute difference (SAD). Incorporated 3:2 and 5:2 adder compressor units (ACU) are used in the processing units to achieve high computational speed and make the architecture compatible for high definition television videos. The adder compressor units are capable of parallel addition of eight addend data. The complete hardware is realized in Verilog HDL, functionally verified, and implemented on FPGA. Also, the design is synthesized using Synopsys RC design compiler of 90nm technology standard cell library as an application specific integrated circuits (ASIC) implementation. Simulation and synthesis results show that the implemented architecture for diamond search algorithm achieve best results when performance evaluation is done.