Design of efficient programmable test-per-scan logic BIST modules

This paper focus on the design of Programmable Logic BIST structures for Very Large Scale Integration (VLSI) Integrated Circuit(IC) testing. The advancements happening in VLSI technology day by day have made chip testing more complicated. This has paved way for the increased popularity of Logic Built In Self Test (LBIST) compared to Automatic Test Equipment (ATE). Logic BIST allows self testing of chips with the help of an additional built-in hardware structure inside the circuit. Test-per-scan Logic BIST structure includes Test pattern generator, Response Analyzer, ROM, and Comparator. LFSR does the role of test pattern generator in Logic BIST since it is more efficient than binary counters. MISR is commonly used as an output response analyzer which acts as an alternative to n-parallel LFSRs. Comparator compares the responses stored in ROM and MISR output. Reconfigurability is added to every structural element in BIST to improve the fault coverage of IC testing. The proposed structural architecture is simulated in Modelsim RTL simulator. The different sized (16, 32, 48) programmable structures in Logic BIST were synthesized in Xilinx Spartan 3E and Spartan 6 for implementing them on FPGA. Four structural representations such as Modular, Standard, Hybrid and Complete form were implemented for PRPG and MISR design. All the designs were synthesized in ASIC in RTL compiler using 90nm standard cell technology library. The results of the proposed programmable PRPG and MISR designs were analyzed for speed, power and area with the equivalent modules generated by third party sign-off tool.