Test suite for SoC interconnect verification

Modern day system-on-chip (SoC) designs have many inbuilt IP cores and it is crucial that the communication between these cores is properly synchronized. This synchronization is ensured by the interconnects based on various bus protocols. Hence, it is crucial to verify these interconnects during the development of such SoCs and this is what takes most of the time as compared to the design stage. But writing test benches each time to verify various protocols would be time consuming, challenging and requires deep knowledge of these protocols and methodology expertise. So nowadays, configurable test benches are used which helps eliminating tedious tasks of developing tests for complex protocols. A test suite is a complete self-contained, configurable environment targeted at the verification of interconnects used in complex SoCs. It is a collection of test cases and sequences written in a generic way aimed at reducing the time for verification. It simplifies integration, enables user customization, and maximizes reuse across projects. This paper shows how the test suite addresses the challenges faced during the verification of interconnects used in complex SoCs. It also involves writing an example test suite sequence and test using the Universal Verification Methodology (UVM) which is a standard verification methodology based on the System Verilog language.