An area efficient termination resistance calibration mechanism for LVDS transceiver in 55nm CMOS

LVDS (Low Voltage Differential signalling) is a protocol used serial communication. Low power and high speed are the key icons of this technology. Moreover the immunity to the noise is very high since LVDS uses the differential method of operation. LVDS technology is used mainly in high speed serial data communication. This includes modern digital communication, digital image processing. In this paper, a resistance calibration mechanism for an LVDS transceiver is introduced. LVDS uses a common mode voltage level of 1.2 V and a swing of 350mV. Thus a 3.5 mA is passed through a 100 ohm on chip resistor to produce a 350mV. The method for keeping the 100Om on chip resistor across all process, voltage and temperature corners is explained in this paper.