A Hybrid arbiter to accelerate performance of high speed soc

To achieve a high performance of a system on chip design we should focus on a faster chip communication architecture based on different arbitration scheme. Where all master requests are having different priority. So designing the arbiter having ability to perform in worst corner cases. This paper is introduction to a modified dynamic bus arbiter based on fuzzy logic for a system on chip design architecture. We are considering the worst case here that all masters are requesting for grant to access the bus, so arbiter need to manages the situation based on information about priority scheme, previously granted master and existing lottery arbitration scheme and fuzzy logic arbitration scheme. So we proposed a new two stage technique for granting the access of data bus by creating a subset of various master on the basis of their priority and using dynamic lottery scheme at first stage and fuzzy logic in the second stage in system. This is process by Acceptance rate calculator to decide which algorithm to resolve the grant issue. A hybrid arbiter which results in removing bus starvation and contention problem. This method is also address the pseudo random number is greater than the total partial sum in modified dynamic arbiter based on lottery manager so for this deciding factor is priority selection method and information about the previously granted master which also help to improve the latency. Also making the physical implementation for the design which give the problems related physical implementation of design which affects the frequency of the design. As current design is operated on the frequency 1.2 GHz, as latest CPU are operating on the frequency of 1.8 GHz.