Pixel correlation based computation and energy reduction techniques for HEVC fractional interpolation

Fractional interpolation is one of the most computationally intensive parts of High Efficiency Video Coding (HEVC). Therefore, in this paper, two pixel correlation based computation and energy reduction techniques for HEVC fractional interpolation are proposed. The proposed pixel equality based computation reduction (PECR) technique does not affect the PSNR and bit-rate. The proposed pixel similarity based computation reduction (PSCR) technique slightly decreases PSNR and increases bit-rate. In this paper, a low energy HEVC fractional (half-pixel and quarter-pixel) interpolation hardware for all prediction unit sizes including the proposed techniques is also designed and implemented using Verilog HDL. The proposed hardware, in the worst case, can process 48 quad HD (2160×1600) video frames per second. The proposed PECR and PSCR techniques reduced the energy consumption of this hardware up to 39.7% and 46.9%, respectively.