Interconnect modeling in deep submicron design

As scaling has continued for more than 20 years, it has yielded faster and denser chips with ever increasing functionality. The scaling will continue down to or beyond 0.1 /spl mu/m as proposed in the SIA Technical Road map. With scaling, device performance improves, however, interconnect performance is degraded. In this scaled deep submicron technology, however, interconnects limit the performance, packing density and yield, if not properly modeled. In order to properly model and design the interconnect-dominated circuits, accurate and proper interconnect modeling is a must to assure the performance and functionality of ever-increasing complex multimillion transistor VLSI circuits. In this paper, the overall flow of interconnect modeling in IC design is reviewed, including interconnect characterization, various 2-D/3-D field solvers, 2-D/3-D interconnect model library generation, and parameter extraction. Then advanced topics of interconnect modeling in deep submicron are reviewed; statistical interconnect modeling, 3-D Monte Carlo simulation for global nets, and 3-D inductance modeling.